1. Field of the Invention
The present invention relates to a voltage converter, and more particularly, to a voltage converter capable of correctly enabling a converting module coupled to an output port of the voltage converter.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram of an example of a prior art flyback voltage converter 100. As shown in FIG. 1, the voltage converter 100 comprises a primary converting module 105 and a secondary converting module 110. The primary converting module 105 has a first electronic induction device L1 and a transistor Q1, and is utilized for storing energy coming from the input port of the voltage converter 100 when the transistor Q1 is turned on by a control signal Sc, and for transferring energy stored in the first electronic induction device L1 to the secondary converting module 110 when the transistor Q1 is turned off by the control signal Sc. The secondary converting module 110 has a second electronic induction device L2 and a rectifying component 112 (implemented in this example by a diode D), and is utilized for transforming energy coming from the primary converting module 105 to generate an output voltage signal Sout. Usually, the voltage converter 100 works in a continuous conduction mode; however, it may work in a discontinuous conduction mode in certain situations, for example, in a situation where the voltage converter 100 only transfers 20 Watts to the output port of the voltage converter 100 even though power coming from the input port of the voltage converter 100 is higher than 20 Watts.
Please refer to FIG. 2 in conjunction with FIG. 1. FIG. 2 is a timing diagram illustrating operation of the prior art voltage converter 100 operating in the continuous conduction mode. As shown in FIG. 2, when the transistor Q1 is turned on, the voltage level V1 remains at a voltage level Vin (i.e. the voltage level of the input voltage signal Sin shown in FIG. 1) and the first electronic induction device L1 is equivalently coupled to the ground voltage level where the voltage level Vds is small and negligible. At this time, the current passing through the first electronic induction device L1 (i.e. I1) increases slowly from zero up to a limit I1max. Once the transistor Q1 is turned off (i.e. at time t1), the voltage level V1 will be switched to another voltage level −(Vout+Vd)*N1/N2 immediately and the voltage level Vds will become another voltage level Vin+(Vout+Vd)*N1/N2, wherein the value N1/N2 is a turns ratio between the first and second electronic induction devices L1, L2, and the voltage Vd is a conduction voltage of the diode D when forward-biased. At this time, the current I1 will become zero and the current passing through the second electronic induction device L2 (i.e. I2) will increase immediately, then decrease slowly from a limit I2max to zero to provide a voltage level of the output voltage signal Sout (i.e. Vout). Therefore, in continuous conduction mode the currents I1, I2 will not become zero at the same time; this does occur, however, in discontinuous conduction mode.
Please refer to FIG. 3. FIG. 3 is a timing diagram illustrating operation of the prior art voltage converter 100 operating in discontinuous conduction mode. As shown in FIG. 3, a difference of the current I2 compared to the current in FIG. 2 is that the current I2 shown in FIG. 3 reaches zero at time t2 and remains at zero during a time period t2˜T. The voltage level Vds will then oscillate during the time period t2˜T due to the parasitic capacitance/inductance within the voltage converter 100 itself. The diode D can still operate correctly even though the operation of the diode D is controlled by the voltage drop across itself and the oscillation of the voltage level Vds also causes the voltage drop across the diode D to oscillate. An only disadvantage is that a power loss is introduced due to the voltage drop across the diode D. In general, a switch device implemented by a transistor is utilized for replacing the operation and function of the diode D in the secondary converting module 110. However, another power loss is introduced since the transistor may operate erroneously.
In general, there are two prior art schemes capable of avoiding the power loss caused by the above-mentioned transistor. One of the prior art schemes detects the current passing through the second electronic induction device L2 (i.e. I2) to control the transistor for avoiding the power loss. This scheme has to add a current sensing resistor or a current sensing transformer in the voltage converter 100, however. Considering total cost of the voltage converter 100, adding a current sensing resistor or current sensing transformer is not desirable.
Another prior art scheme capable of avoiding the power loss directly detects the waveform of the voltage level between the second electronic induction device L2. Please refer to FIG. 4. FIG. 4 is a diagram of an example of a prior art flyback voltage converter 400 capable of avoiding the power loss. As shown in FIG. 4, the voltage converter 400 comprises a primary converting module 405, a secondary converting module 410, and a synchronous rectification controller 415. The secondary converting module 410 comprises a second electronic induction device L2 and a switch device (in this example, it is implemented by a transistor Q2). The synchronous rectification controller 415 is utilized for generating a control signal Vc to control an on/off status of the transistor Q2 in the secondary converting module 410 by directly detecting the waveform of the voltage level at the node Z shown in FIG. 4.
Please refer to FIG. 5. FIG. 5 is a timing diagram illustrating operation of the prior art voltage converter 400 operating in the discontinuous conduction mode. As shown in FIG. 5, for example, when the control signal Sc remains at a high logic level during a time period t1˜t2, the transistor Q1 in the primary converting module 405 shown in FIG. 4 is turned on. The node Z shown in FIG. 4 is regarded as a floating node since the status of the transistor Q2 remains off. The voltage level at the node Z (i.e. Vz) then remains at a high voltage level during the time period t1˜t2. At time t2, the second electronic induction device L2 will be discharged for providing a stable voltage level of the output voltage signal Sout. The voltage level Vz will be decreased to zero Volts immediately since the transistor Q1 will be turned off. Once the synchronous rectification controller 415 detects an immediately decreased voltage level Vz from the high voltage level to zero Volts, the transistor Q2 is turned on by the synchronous rectification controller 415. Therefore, the second electronic induction device L2 starts discharging for providing the stable voltage level of the output voltage signal Sout until time t3, and the synchronous rectification controller 415 can control the status of the transistor Q2 by detecting the immediately decreased voltage level Vz. In general, detecting the immediately decreased voltage level Vz is implemented by detecting a transition of the voltage level Vz from the high voltage level to a low voltage level based on a reference voltage level Vref. The voltage level Vz may be unstable (i.e. the voltage level Vz may oscillate) during a time period t3˜t5, however, since the node Z is regarded as a floating node as mentioned above. It is possible for the synchronous rectification controller 415 to detect a transition of the unstable voltage level Vz and thus the transistor Q2 is erroneously turned on by the synchronous rectification controller 415. For example, the transistor Q2 is erroneously conducted in a time period t4˜t5 shown in FIG. 5. This will cause another problem for detecting the voltage level Vz to control the transistor Q2. Therefore, controlling the transistor Q2 only by detecting a transition of the voltage level Vz based on the reference voltage level Vref has some disadvantages.
For solving the above-mentioned problem, the prior art scheme further generates a sensor pulse according to a plurality of predetermined levels VA, VB and a transition of the voltage level Vz from the high voltage level to the low voltage level. The sensor pulse and a reference pulse will be compared to determine whether the transition of the voltage level Vz is stable (i.e. the voltage level Vz does not oscillate at this time). Please refer to FIG. 6. FIG. 6 is a diagram illustrating two operation results of the prior art voltage converter 400 according to different transitions of the voltage level Vz and the reference pulse. As shown in FIG. 6, the left part of this diagram shows operation of the voltage converter 400 under the condition of a transition of an unstable voltage level Vz, while the right part of this diagram shows operation of the voltage converter 400 under the condition of a transition of a stable voltage level Vz′. Usually, a transition time of the unstable voltage level Vz is much longer than that of the stable voltage level Vz′. For example, the transition time of the unstable voltage level Vz from a high voltage level VA to a low voltage level VB may be up to 250 nanoseconds, yet the transition time of the stable voltage level Vz′ from the high voltage level VA to the low voltage level VB is only up to 50 nanoseconds. The synchronous rectification controller 415 can turn on the transistor Q2 correctly by the sensor pulses TAB, TAB′ and the reference pulse Tref. For example, the synchronous rectification controller 415 turns on the transistor Q2 when it detects that the width of the sensor pulse TAB′ is shorter than that of the reference pulse Tref, and turns the transistor Q2 off when detecting that the width of the sensor pulse TAB is longer than that of the reference pulse Tref. A primary defect of utilizing the above-mentioned sensor pulses is that the voltage level at the node Z in this voltage converter may be slightly different from that in another voltage converter. It is very possible that the sensor pulse TAB′ does not correspond to a period when the voltage level Vz′ transits from the predetermined level VA to the predetermined level VB (i.e. the period that the voltage level Vz′ changes very sharply). If serious enough, a stable waveform of the voltage level at the node Z could be erroneously regarded as an unstable waveform. For instance, a stable waveform of a voltage level at the node Z in a different voltage converter could be regarded as an unstable waveform since the predetermined level VA may be changed due to process drift. Another defect of the sensor pulses is that a starting timing of a pulse utilized for conducting the transistor Q2 of FIG. 4 is later than an ending timing of the reference pulse Tref. However, during the reference pulse Tref, the transistor Q2 may be turned on by its body diode voltage even though the control signal Vc generated from the synchronous rectification controller 415 is zero. Thus additional power dissipation may be introduced.
The present invention provides a new scheme for solving the above-mentioned problems in the discontinuous conduction mode without generation and comparison of the sensor pulse and the reference pulse.